SM83 Cells Reference

This document provides information about the cells found in the SM83 CPU core of the Game Boy.

Please report any errors I made here.

• Basic logic gates
  • INVERTER gates
    • INV_IDU
    • INV_IRQ
    • INV_REG
    • INV_REG_A_WR
    • INV_REG_B_WR
    • INV_REG_H_E_WR
    • INV_REG_IE_WR
    • INV_REG_L_WR
    • INV_REG_PC_WR
    • INV_REG_SP_WR
    • INV_REG_WR
  • INVERTER gates with precharge
    • INV_ALU - Variant A
    • INV_ALU - Variant B
    • INV_DEC3 - Variant A
    • INV_DEC3 - Variant A2
    • INV_DEC3 - Variant B
    • INV_DEC3 - Variant B2
    • INV_DEC3 - Variant C
  • NAND gates
    • NAND2_NAND3_IRQ
    • REG_A_OUT
  • NOR gates with precharge
    • NOR2_DEC3
  • AND gates
    • AND_REG
    • AND2_AND3_REG
  • XOR gates
    • XOR_IDU_H
    • XOR_IDU_L
• Compound logic gates
  • OA_REG
  • MUX_IDU_H
  • MUX_IDU_L
• Mixed logic cells
  • IDU_BIT0
  • IDU_BIT123456
  • IDU_BIT7
  • IDU_IRQ_CTL
  • IRQ_PRIO_BIT0
  • IRQ_PRIO_BIT1
  • IRQ_PRIO_BIT2
  • IRQ_PRIO_BIT3
  • IRQ_PRIO_BIT4
  • IRQ_PRIO_BIT5
  • IRQ_PRIO_BIT6
  • IRQ_PRIO_BIT7
  • NOR2_INV_REG
  • REG_BC_OUT
  • REG_BUS_PCH_A_BIT0123
  • REG_BUS_PCH_A_BIT4
  • REG_BUS_PCH_A_BIT5
  • REG_BUS_PCH_A_BIT6
  • REG_BUS_PCH_A_BIT7
  • REG_BUS_PCH_B
  • REG_DE_OUT
  • REG_HL_OUT
  • REG_PC_OUT_BIT012
  • REG_PC_OUT_BIT345
  • REG_PC_OUT_BIT67
  • REG_SP_OUT
  • REG_WZ_OUT
• Storage elements
  • D_LATCH_IRQ
  • DFF_ALU_FLAG
  • DFF_ALU_TMP
  • DFF_REG_BIT - Variant A
  • DFF_REG_BIT - Variant B
  • DFF_REG_SP_BIT
  • DFF_REG_WZ_BIT
  • DRFF_REG_IE_BIT
  • DSFF_REG_PC_BIT

Basic logic gates

INVERTER gates

INV_IDU

Two simple inverters.

I/O Description A_IN Input to inverter A. A_Q Outputs inverted A_IN. B_IN Input to inverter B. B_Q Outputs inverted B_IN.

Instances: IDU_INV[0], IDU_INV[1], IDU_INV[2], IDU_INV[3], IDU_INV[4], IDU_INV[5], IDU_INV[6], IDU_INV[7] (8 total)

INV_IRQ

Five simple inverters.

I/O Description A_IN Input to inverter A. A_Q Outputs inverted A_IN. B_IN Input to inverter B. B_Q Outputs inverted B_IN. C_IN Input to inverter C. C_Q Outputs inverted C_IN. D_IN Input to inverter D. D_Q Outputs inverted D_IN. E_IN Input to inverter E. E_Q Outputs inverted E_IN.

Instances: IRQ_INV (1 total)

INV_REG

Simple inverter.

I/O Description IN Input to inverter. Q Outputs inverted IN.

Instances: REG_INV[0], REG_INV[1], REG_INV[2], REG_INV[3], REG_INV[4], REG_INV[5], REG_INV[6], REG_INV[7] (8 total)

INV_REG_A_WR

Simple inverter.

I/O Description IN Input to inverter. Q Outputs inverted IN.

Instances: INV_A_WR (1 total)

INV_REG_B_WR

Simple inverter.

I/O Description IN Input to inverter. Q Outputs inverted IN.

Instances: INV_B_WR (1 total)

INV_REG_H_E_WR

Simple inverter.

I/O Description IN Input to inverter. Q Outputs inverted IN.

Instances: INV_E_WR, INV_H_WR (2 total)

INV_REG_IE_WR

Simple inverter.

I/O Description IN Input to inverter. Q Outputs inverted IN.

Instances: INV_IE_WR (1 total)

INV_REG_L_WR

Simple inverter.

I/O Description IN Input to inverter. Q Outputs inverted IN.

Instances: INV_L_WR (1 total)

INV_REG_PC_WR

Two simple inverters.

I/O Description A_IN Input to inverter A. A_Q Outputs inverted A_IN. B_IN Input to inverter B. B_Q Outputs inverted B_IN.

Instances: INV_PCH_WR, INV_PCL_WR (2 total)

INV_REG_SP_WR

Simple inverter.

I/O Description IN Input to inverter. Q Outputs inverted IN.

Instances: INV_SPH_WR, INV_SPL_WR (2 total)

INV_REG_WR

Simple inverter.

I/O Description IN Input to inverter. Q Outputs inverted IN.

Instances: INV_C_WR, INV_D_WR, INV_IR_WR, INV_W_WR, INV_Z_WR (5 total)

INVERTER gates with precharge

INV_ALU - Variant A

Inverter with precharge.

I/O Description IN Input to inverter. Outputs high if PCH is low. Q Outputs inverted IN. PCH Active-low precharge input. If low, IN gets driven high for the purpose of precharging the net connected to the input.

Instances: ALU_INV1, ALU_INV2, ALU_INV3, ALU_INV4, ALU_INV5, ALU_INV6, ALU_INV7, ALU_INV8, ALU_INV10 (9 total)

INV_ALU - Variant B

Inverter with precharge.

I/O Description IN Input to inverter. Outputs high if PCH is low. Q Outputs inverted IN. PCH Active-low precharge input. If low, IN gets driven high for the purpose of precharging the net connected to the input.

Instances: ALU_INV9 (1 total)

INV_DEC3 - Variant A

Inverter with precharge.

I/O Description IN Input to inverter. Outputs high if PCH is low. Q Outputs inverted IN. PCH Active-low precharge input. If low, IN gets driven high for the purpose of precharging the net connected to the input.

Instances: DEC3_INV1, DEC3_INV2, DEC3_INV3, DEC3_INV4, DEC3_INV5, DEC3_INV6, DEC3_INV7, DEC3_INV8, DEC3_INV9, DEC3_INV10, DEC3_INV11, DEC3_INV12, DEC3_INV13, DEC3_INV14, DEC3_INV15, DEC3_INV17, DEC3_INV18, DEC3_INV19, DEC3_INV20, DEC3_INV21, DEC3_INV22, DEC3_INV25, DEC3_INV32, DEC3_INV33, DEC3_INV42, DEC3_INV43, DEC3_INV44, DEC3_INV45, DEC3_INV46, DEC3_INV53, DEC3_INV58, DEC3_INV59, DEC3_INV60, DEC3_INV61, DEC3_INV62, DEC3_INV63, DEC3_INV64, DEC3_INV65, DEC3_INV66, DEC3_INV67 (40 total)

INV_DEC3 - Variant A2

Inverter with precharge.

I/O Description IN Input to inverter. Outputs high if PCH is low. Q Outputs inverted IN. PCH Active-low precharge input. If low, IN gets driven high for the purpose of precharging the net connected to the input.

Instances: DEC3_INV24, DEC3_INV31, DEC3_INV37 (3 total)

INV_DEC3 - Variant B

Inverter with precharge.

I/O Description IN Input to inverter. Outputs high if PCH is low. Q Outputs inverted IN. PCH Active-low precharge input. If low, IN gets driven high for the purpose of precharging the net connected to the input.

Instances: DEC3_INV16, DEC3_INV30, DEC3_INV49, DEC3_INV50, DEC3_INV51, DEC3_INV52, DEC3_INV56 (7 total)

INV_DEC3 - Variant B2

Inverter with precharge.

I/O Description IN Input to inverter. Outputs high if PCH is low. Q Outputs inverted IN. PCH Active-low precharge input. If low, IN gets driven high for the purpose of precharging the net connected to the input.

Instances: DEC3_INV29, DEC3_INV38, DEC3_INV39, DEC3_INV40, DEC3_INV41 (5 total)

INV_DEC3 - Variant C

Inverter with precharge.

I/O Description IN Input to inverter. Outputs high if PCH is low. Q Outputs inverted IN. PCH Active-low precharge input. If low, IN gets driven high for the purpose of precharging the net connected to the input.

Instances: DEC3_INV23, DEC3_INV26, DEC3_INV27, DEC3_INV28, DEC3_INV34, DEC3_INV35, DEC3_INV36, DEC3_INV47, DEC3_INV48, DEC3_INV54, DEC3_INV55, DEC3_INV57 (12 total)

NAND gates

NAND2_NAND3_IRQ

NAND with two inputs and open-drain NAND with three inputs.

I/O Description A_IN1, A_IN2 Inputs to NAND gate A. A_Q Outputs !(A_IN1 && A_IN2). B_IN1, B_IN2, B_IN3 Inputs to NAND gate B. B_Q Open-drain output. Outputs !(B_IN1 && B_IN2 && B_IN3).

Instances: IRQ_NAND2_NAND3[0], IRQ_NAND2_NAND3[1], IRQ_NAND2_NAND3[2], IRQ_NAND2_NAND3[3], IRQ_NAND2_NAND3[4], IRQ_NAND2_NAND3[5], IRQ_NAND2_NAND3[6], IRQ_NAND2_NAND3[7] (8 total)

REG_A_OUT

Output drivers for A registers.

I/O Description A_ENA Input to NAND gate A. B_ENA Input to NAND gate B. IN Input to both NAND gates. A_Q Open-drain output. Outputs !(A_ENA && IN). B_Q Open-drain output. Outputs !(B_ENA && IN).

Instances: REG_A_OUT[0], REG_A_OUT[1], REG_A_OUT[2], REG_A_OUT[3], REG_A_OUT[4], REG_A_OUT[5], REG_A_OUT[6], REG_A_OUT[7] (8 total)

NOR gates with precharge

NOR2_DEC3

NOR gate with two inputs and precharge on input 1.

I/O Description IN1 Input to NOR gate. Outputs high if PCH is low. IN2 Input to NOR gate. Q Outputs !(IN1 || IN2). PCH Active-low precharge input. If low, IN1 gets driven high for the purpose of precharging the net connected to the input.

Instances: DEC3_NOR1, DEC3_NOR2 (2 total)

AND gates

AND_REG

AND gate with two inputs.

I/O Description IN1, IN2 Inputs to AND gate. Q Outputs (IN1 && IN2).

Instances: REG_AND (1 total)

AND2_AND3_REG

Group of two AND gates with two and three inputs.

I/O Description A_IN1, A_IN2 Inputs to AND gate A. A_Q Outputs (A_IN1 && A_IN2). B_IN1, B_IN2, B_IN3 Inputs to AND gate B. B_Q Outputs (B_IN1 && B_IN2 && B_IN3).

Instances: REG_AND2_AND3 (1 total)

XOR gates

XOR_IDU_H

XOR gate with two inputs.

There is one external connection always made on this cell (see orange line in the picture) that is required to connect the two IN1 inputs.

I/O Description IN1, IN2 Inputs to XOR gate. There are two IN1 inputs to this cell, which are externally connected to each other (indicated by the orange line in the picture). Q Outputs (IN1 ^ IN2).

Instances: IDU_XOR_H[0], IDU_XOR_H[1], IDU_XOR_H[2], IDU_XOR_H[3], IDU_XOR_H[4], IDU_XOR_H[5], IDU_XOR_H[6], IDU_XOR_H[7] (8 total)

XOR_IDU_L

XOR gate with two inputs.

I/O Description IN1, IN2 Inputs to XOR gate. Q Outputs (IN1 ^ IN2).

Instances: IDU_XOR_L[0], IDU_XOR_L[1], IDU_XOR_L[2], IDU_XOR_L[3], IDU_XOR_L[4], IDU_XOR_L[5], IDU_XOR_L[6], IDU_XOR_L[7] (8 total)

Compound logic gates

OA_REG

2-1 OR-AND two-level compound gate.

I/O Description IN1, IN2 Inputs to OR gate. IN3 Input to AND gate. Q Outputs ((IN1 || IN2) && IN3).

Instances: REG_OA1, REG_OA2 (2 total)

MUX_IDU_H

Multiplexer with two inputs.

There is one external connection always made on this cell (see orange line in the picture) that is required to connect the two SEL inputs.

I/O Description D0, D1 Data inputs. SEL Select input. There are two SEL inputs to this cell, which are externally connected to each other (indicated by the orange line in the picture). Q Outputs D1 if SEL is high; outputs D0 if SEL is low.

Instances: IDU_MUX_H[0], IDU_MUX_H[1], IDU_MUX_H[2], IDU_MUX_H[3], IDU_MUX_H[4], IDU_MUX_H[5], IDU_MUX_H[6], IDU_MUX_H[7] (8 total)

MUX_IDU_L

Multiplexer with two inputs.

There is one external connection always made on this cell (see orange line in the picture) that is required to connect the two SEL inputs.

I/O Description D0, D1 Data inputs. SEL Select input. There are two SEL inputs to this cell, which are externally connected to each other (indicated by the orange line in the picture). Q Outputs D1 if SEL is high; outputs D0 if SEL is low.

Instances: IDU_MUX_L[0], IDU_MUX_L[1], IDU_MUX_L[2], IDU_MUX_L[3], IDU_MUX_L[4], IDU_MUX_L[5], IDU_MUX_L[6], IDU_MUX_L[7] (8 total)

Mixed logic cells

IDU_BIT0

Bits 0 and 8 of the 16 bit increment/decrement unit.

I/O Description   TODO: Describe I/Os

Instances: IDU[0] (1 total)

IDU_BIT123456

Bits 1-6 and 9-14 of the 16 bit increment/decrement unit.

I/O Description   TODO: Describe I/Os

Instances: IDU[1] IDU[2] IDU[3] IDU[4] IDU[5] IDU[6] (6 total)

IDU_BIT7

Bits 7 and 15 of the 16 bit increment/decrement unit.

I/O Description   TODO: Describe I/Os

Instances: IDU[7] (1 total)

IDU_IRQ_CTL

Logic for increment/decrement unit and interrupts.

I/O Description   TODO: Describe I/Os

Instances: IDU_IRQ_CTL (1 total)

IRQ_PRIO_BIT0

Interrupt priority decoding and other interrupt related logic.

Instances: IRQ_PRIO[0] (1 total)

IRQ_PRIO_BIT1

Interrupt priority decoding and other interrupt related logic.

Instances: IRQ_PRIO[1] (1 total)

IRQ_PRIO_BIT2

Interrupt priority decoding and other interrupt related logic.

Instances: IRQ_PRIO[2] (1 total)

IRQ_PRIO_BIT3

Interrupt priority decoding and other interrupt related logic.

Instances: IRQ_PRIO[3] (1 total)

IRQ_PRIO_BIT4

Interrupt priority decoding and other interrupt related logic.

Instances: IRQ_PRIO[4] (1 total)

IRQ_PRIO_BIT5

Interrupt priority decoding and other interrupt related logic.

Instances: IRQ_PRIO[5] (1 total)

IRQ_PRIO_BIT6

Interrupt priority decoding and other interrupt related logic.

Instances: IRQ_PRIO[6] (1 total)

IRQ_PRIO_BIT7

Interrupt priority decoding and other interrupt related logic.

Instances: IRQ_PRIO[7] (1 total)

NOR2_INV_REG

NOR gate with two inputs and two inverters.

I/O Description IN1 Input to NOR/OR gate and inverter. IN2 Input to NOR/OR gate. NOR_Q Outputs !(IN1 || IN2). OR_Q Outputs (IN1 || IN2). INV_Q Outputs inverted IN1.

Instances: REG_NOR2_INV (1 total)

REG_BC_OUT

Output drivers for BC registers.

I/O Description B_IN Input to NAND gate B and AOI gate. C_IN Input to NAND gate C and AOI gate. ENA1 Input to both NAND gates. B_ENA2, C_ENA2 Inputs to AOI gate. B_Q1 Open-drain output. Outputs !(ENA1 && B_IN). C_Q1 Open-drain output. Outputs !(ENA1 && C_IN). Q2 Open-drain output. Outputs !((B_ENA2 && B_IN) || (C_ENA2 && C_IN)).

Instances: REG_BC_OUT[0], REG_BC_OUT[1], REG_BC_OUT[2], REG_BC_OUT[3], REG_BC_OUT[4], REG_BC_OUT[5], REG_BC_OUT[6], REG_BC_OUT[7] (8 total)

REG_BUS_PCH_A_BIT0123

Precharger and zero output for register busses bits 0-3.

There is one external connection always made on this cell (see orange line in the picture) that is required to connect the two PCH inputs.

I/O Description PCH Active-low precharge input. If low, outputs A_Q, B_Q and C_Q get driven high for the purpose of precharging their respective nets. There are two PCH inputs to this cell, which are externally connected to each other (indicated by the orange line in the picture). C_ZERO If C_ZERO and PCH are both high, C_Q outputs 0. A_Q Open-source output. Outputs high if PCH is low. B_Q Open-source output. Outputs high if PCH is low. B_Q Outputs inverted B_Q. C_Q Outputs low if C_ZERO and PCH are both high. Outputs high if PCH is low. C_Q Outputs inverted C_Q.

Instances: REG_BUS_PCH_A[0], REG_BUS_PCH_A[1], REG_BUS_PCH_A[2], REG_BUS_PCH_A[3] (4 total)

REG_BUS_PCH_A_BIT4

Precharger and zero output for register busses bit 4.

There is one external connection always made on this cell (see orange line in the picture) that is required to connect the two PCH inputs.

I/O Description PCH Active-low precharge input. If low, outputs A_Q, B_Q and C_Q get driven high for the purpose of precharging their respective nets. There are two PCH inputs to this cell, which are externally connected to each other (indicated by the orange line in the picture). C_ZERO_A If C_ZERO_A and PCH are both high, C_Q outputs 0. C_ZERO_B1, C_ZERO_B2 If C_ZERO_B1, C_ZERO_B2 and PCH are high, C_Q outputs 0. A_Q Open-source output. Outputs high if PCH is low. B_Q Open-source output. Outputs high if PCH is low. B_Q Outputs inverted B_Q. C_Q Outputs low if ((C_ZERO_A || (C_ZERO_B1 && C_ZERO_B2)) && PCH) is true. Outputs high if PCH is low. C_Q Outputs inverted C_Q.

Instances: REG_BUS_PCH_A[4] (1 total)

REG_BUS_PCH_A_BIT5

Precharger and zero output for register busses bit 5.

There is one external connection always made on this cell (see orange line in the picture) that is required to connect the two PCH inputs.

I/O Description PCH Active-low precharge input. If low, outputs A_Q, B_Q and C_Q get driven high for the purpose of precharging their respective nets. There are two PCH inputs to this cell, which are externally connected to each other (indicated by the orange line in the picture). C_ZERO_A If C_ZERO_A and PCH are both high, C_Q outputs 0. C_ZERO_B1, C_ZERO_B2 If C_ZERO_B1, C_ZERO_B2 and PCH are high, C_Q outputs 0. A_Q Open-source output. Outputs high if PCH is low. B_Q Open-source output. Outputs high if PCH is low. B_Q Outputs inverted B_Q. C_Q Outputs low if ((C_ZERO_A || (C_ZERO_B1 && C_ZERO_B2)) && PCH) is true. Outputs high if PCH is low. C_Q Outputs inverted C_Q.

Instances: REG_BUS_PCH_A[5] (1 total)

REG_BUS_PCH_A_BIT6

Precharger and zero output for register busses bit 6.

There is one external connection always made on this cell (see orange line in the picture) that is required to connect the two PCH inputs.

I/O Description PCH Active-low precharge input. If low, outputs A_Q, B_Q and C_Q get driven high for the purpose of precharging their respective nets. There are two PCH inputs to this cell, which are externally connected to each other (indicated by the orange line in the picture). C_ZERO_A If C_ZERO_A and PCH are both high, C_Q outputs 0. C_ZERO_B1, C_ZERO_B2 If C_ZERO_B1, C_ZERO_B2 and PCH are high, C_Q outputs 0. A_Q Open-source output. Outputs high if PCH is low. B_Q Open-source output. Outputs high if PCH is low. B_Q Outputs inverted B_Q. C_Q Outputs low if ((C_ZERO_A || (C_ZERO_B1 && C_ZERO_B2)) && PCH) is true. Outputs high if PCH is low. C_Q Outputs inverted C_Q.

Instances: REG_BUS_PCH_A[6] (1 total)

REG_BUS_PCH_A_BIT7

Precharger and zero output for register busses bit 7.

There is one external connection always made on this cell (see orange line in the picture) that is required to connect the two PCH inputs.

I/O Description PCH Active-low precharge input. If low, outputs A_Q, B_Q and C_Q get driven high for the purpose of precharging their respective nets. There are two PCH inputs to this cell, which are externally connected to each other (indicated by the orange line in the picture). C_ZERO_A If C_ZERO_A and PCH are both high, C_Q outputs 0. C_ZERO_B1, C_ZERO_B2 If C_ZERO_B1, C_ZERO_B2 and PCH are high, C_Q outputs 0. A_Q Open-source output. Outputs high if PCH is low. B_Q Open-source output. Outputs high if PCH is low. B_Q Outputs inverted B_Q. C_Q Outputs low if ((C_ZERO_A || (C_ZERO_B1 && C_ZERO_B2)) && PCH) is true. Outputs high if PCH is low. C_Q Outputs inverted C_Q.

Instances: REG_BUS_PCH_A[7] (1 total)

REG_BUS_PCH_B

Precharger for register busses.

I/O Description PCH Active-low precharge input. If low, outputs A_Q and B_Q get driven high for the purpose of precharging their respective nets. A_Q Open-source output. Outputs high if PCH is low. B_Q Open-source output. Outputs high if PCH is low.

Instances: REG_BUS_PCH_B[0], REG_BUS_PCH_B[1], REG_BUS_PCH_B[2], REG_BUS_PCH_B[3], REG_BUS_PCH_B[4], REG_BUS_PCH_B[5], REG_BUS_PCH_B[6], REG_BUS_PCH_B[7] (8 total)

REG_DE_OUT

Output drivers for DE registers.

I/O Description D_IN Input to NAND gate D and AOI gate. E_IN Input to NAND gate E and AOI gate. ENA1 Input to both NAND gates. D_ENA2, E_ENA2 Inputs to AOI gate. D_ZERO1, D_ZERO2 If D_ZERO1 or D_ZERO2 is high, D_Q1 outputs 0. D_Q1 Open-drain output. Outputs (!(ENA1 && D_IN) && !D_ZERO1 && !D_ZERO2). E_Q1 Open-drain output. Outputs !(ENA1 && E_IN). Q2 Open-drain output. Outputs !((D_ENA2 && D_IN) || (E_ENA2 && E_IN)).

Instances: REG_DE_OUT[0], REG_DE_OUT[1], REG_DE_OUT[2], REG_DE_OUT[3], REG_DE_OUT[4], REG_DE_OUT[5], REG_DE_OUT[6], REG_DE_OUT[7] (8 total)

REG_HL_OUT

Output drivers for HL registers.

I/O Description   TODO: Describe I/Os

Instances: REG_HL_OUT[0], REG_HL_OUT[1], REG_HL_OUT[2], REG_HL_OUT[3], REG_HL_OUT[4], REG_HL_OUT[5], REG_HL_OUT[6], REG_HL_OUT[7] (8 total)

REG_PC_OUT_BIT012

Output drivers for PC register bits 0-2.

I/O Description   TODO: Describe I/Os

Instances: REG_PC_OUT[0], REG_PC_OUT[1], REG_PC_OUT[2] (3 total)

REG_PC_OUT_BIT345

Output drivers for PC register bits 3-5.

I/O Description   TODO: Describe I/Os

Instances: REG_PC_OUT[3], REG_PC_OUT[4], REG_PC_OUT[5] (3 total)

REG_PC_OUT_BIT67

Output drivers for PC register bits 6 and 7.

I/O Description   TODO: Describe I/Os

Instances: REG_PC_OUT[6], REG_PC_OUT[7] (2 total)

REG_SP_OUT

Output drivers for SP registers.

I/O Description   TODO: Describe I/Os

Instances: REG_SP_OUT[0], REG_SP_OUT[1], REG_SP_OUT[2], REG_SP_OUT[3], REG_SP_OUT[4], REG_SP_OUT[5], REG_SP_OUT[6], REG_SP_OUT[7] (8 total)

REG_WZ_OUT

Output drivers for WZ registers.

Instances: REG_WZ_OUT[0], REG_WZ_OUT[1], REG_WZ_OUT[2], REG_WZ_OUT[3], REG_WZ_OUT[4], REG_WZ_OUT[5], REG_WZ_OUT[6], REG_WZ_OUT[7] (8 total)

Storage elements

D_LATCH_IRQ

Gated data latch with additionally gated inverted output.

I/O Description D Data input. ENA Active-high enable input. When high, the value at D transparently propagates through the latch. As soon as ENA goes low, the output of the latch gets held at the level it had in that moment until ENA goes high again. ENA Active-low enable input. Must always be the inverse of ENA. Q Data output. Q Inverted data output. GATED_Q Dynamically gated inverted data output. Outputs Q when ENA_Q is low, otherwise outputs low. Needs to be precharged regularly by pulling PCH low and making ENA_Q hi-Z at the same time. ENA_Q Active-low enable input for dynamically gated GATED_Q output. Must be undriven (hi-Z) when PCH is enabled/low. PCH Active-low precharge input. If low, GATED_Q gets driven low. Must be disabled/high when ENA_Q is enabled/low.

Instances: IRQ_LATCH[0], IRQ_LATCH[1], IRQ_LATCH[2], IRQ_LATCH[3], IRQ_LATCH[4], IRQ_LATCH[5], IRQ_LATCH[6], IRQ_LATCH[7] (8 total)

DFF_ALU_FLAG

Negative-edge-triggered semi-dynamic data flip-flop with precharge.

I/O Description D Data input. Gets stored in the flip-flop when CLK and LOAD are both high. However, the new data is only visible at the outputs Q and Q after a negative edge on CLK. Outputs high if PCH is low. PCH Active-low precharge input. If low, D gets driven high for the purpose of precharging the net connected to the input. CLK Clock input. Edge sensitive for presenting stored data at output; level sensitive for taking new data from input into storage. When CLK and LOAD are both high, the data input D gets stored in the flip-flop. After a negative edge on CLK, the newly stored data is visible at the outputs Q and Q. CLK must not be held high for an extended amount of time, otherwise the stored data will decay. LOAD Active-high load input. Input D gets stored in the flip-flop when LOAD and CLK are both high. LOAD Active-low load input. Must always be the inverse of LOAD. Q Data output. Q Inverted data output.

Instances: FLAG_C, FLAG_H, FLAG_N, FLAG_Z (4 total)

DFF_ALU_TMP

Negative-edge-triggered semi-dynamic data flip-flop without inverted output.

I/O Description D Data input. Gets stored in the flip-flop when CLK and LOAD are both high. However, the new data is only visible at the output Q after a negative edge on CLK. CLK Clock input. Edge sensitive for presenting stored data at output; level sensitive for taking new data from input into storage. When CLK and LOAD are both high, the data input D gets stored in the flip-flop. After a negative edge on CLK, the newly stored data is visible at the output Q. CLK must not be held high for an extended amount of time, otherwise the stored data will decay. LOAD Active-high load input. Input D gets stored in the flip-flop when LOAD and CLK are both high. LOAD Active-low load input. Must always be the inverse of LOAD. Q Data output.

Instances: ALU_DFF (1 total)

DFF_REG_BIT - Variant A

Single-edge-triggered semi-dynamic data flip-flop without inverted output.

I/O Description D Data input. Gets stored in the flip-flop when CLK is low and LOAD is high. However, the new data is only visible at the output Q after a positive edge on CLK. CLK Positive clock input. Edge sensitive for presenting stored data at output; level sensitive for taking new data from input into storage. When CLK is low and LOAD is high, the data input D gets stored in the flip-flop. After a positive edge on CLK, the newly stored data is visible at the output Q. CLK must not be held low for an extended amount of time, otherwise the stored data will decay. CLK Negative clock input. Must always be the inverse of CLK. LOAD Active-high load input. Input D gets stored in the flip-flop when LOAD is high and CLK is low. LOAD Active-low load input. Must always be the inverse of LOAD. Q Data output.

Instances: REG_B[0], REG_B[1], REG_B[2], REG_B[3], REG_B[4], REG_B[5], REG_B[6], REG_B[7], REG_C[0], REG_C[1], REG_C[2], REG_C[3], REG_C[4], REG_C[5], REG_C[6], REG_C[7], REG_D[0], REG_D[1], REG_D[2], REG_D[3], REG_D[4], REG_D[5], REG_D[6], REG_D[7], REG_E[0], REG_E[1], REG_E[2], REG_E[3], REG_E[4], REG_E[5], REG_E[6], REG_E[7], REG_H[0], REG_H[1], REG_H[2], REG_H[3], REG_H[4], REG_H[5], REG_H[6], REG_H[7], REG_L[0], REG_L[1], REG_L[2], REG_L[3], REG_L[4], REG_L[5], REG_L[6], REG_L[7] (48 total)

DFF_REG_BIT - Variant B

Single-edge-triggered semi-dynamic data flip-flop with higher driving strength and without inverted output.

In comparison to variant A, this variant (B) has wider output transistors and therefore a higher driving strength. Other than that, both variants are identical.

I/O Description D Data input. Gets stored in the flip-flop when CLK is low and LOAD is high. However, the new data is only visible at the output Q after a positive edge on CLK. CLK Positive clock input. Edge sensitive for presenting stored data at output; level sensitive for taking new data from input into storage. When CLK is low and LOAD is high, the data input D gets stored in the flip-flop. After a positive edge on CLK, the newly stored data is visible at the output Q. CLK must not be held low for an extended amount of time, otherwise the stored data will decay. CLK Negative clock input. Must always be the inverse of CLK. LOAD Active-high load input. Input D gets stored in the flip-flop when LOAD is high and CLK is low. LOAD Active-low load input. Must always be the inverse of LOAD. Q Data output.

Instances: REG_A[0], REG_A[1], REG_A[2], REG_A[3], REG_A[4], REG_A[5], REG_A[6], REG_A[7], REG_IR[0], REG_IR[1], REG_IR[2], REG_IR[3], REG_IR[4], REG_IR[5], REG_IR[6], REG_IR[7] (16 total)

DFF_REG_SP_BIT

Single-edge-triggered semi-dynamic data flip-flop with precharge.

I/O Description D Data input. Gets stored in the flip-flop when CLK is low and LOAD is high. However, the new data is only visible at the outputs Q and Q after a positive edge on CLK. Outputs high if PCH is low. PCH Active-low precharge input. If low, D gets driven high for the purpose of precharging the net connected to the input. CLK Positive clock input. Edge sensitive for presenting stored data at output; level sensitive for taking new data from input into storage. When CLK is low and LOAD is high, the data input D gets stored in the flip-flop. After a positive edge on CLK, the newly stored data is visible at the outputs Q and Q. CLK must not be held low for an extended amount of time, otherwise the stored data will decay. CLK Negative clock input. Must always be the inverse of CLK. LOAD Active-high load input. Input D gets stored in the flip-flop when LOAD is high and CLK is low. LOAD Active-low load input. Must always be the inverse of LOAD. Q Data output. Q Inverted data output.

Instances: REG_SPH[0], REG_SPH[1], REG_SPH[2], REG_SPH[3], REG_SPH[4], REG_SPH[5], REG_SPH[6], REG_SPH[7], REG_SPL[0], REG_SPL[1], REG_SPL[2], REG_SPL[3], REG_SPL[4], REG_SPL[5], REG_SPL[6], REG_SPL[7] (16 total)

DFF_REG_WZ_BIT

Single-edge-triggered semi-dynamic data flip-flop without non-inverted output.

I/O Description D Data input. Gets stored in the flip-flop when CLK is low and LOAD is high. However, the new data is only visible at the output Q after a positive edge on CLK. CLK Positive clock input. Edge sensitive for presenting stored data at output; level sensitive for taking new data from input into storage. When CLK is low and LOAD is high, the data input D gets stored in the flip-flop. After a positive edge on CLK, the newly stored data is visible at the output Q. CLK must not be held low for an extended amount of time, otherwise the stored data will decay. CLK Negative clock input. Must always be the inverse of CLK. LOAD Active-high load input. Input D gets stored in the flip-flop when LOAD is high and CLK is low. LOAD Active-low load input. Must always be the inverse of LOAD. Q Inverted data output.

Instances: REG_W[0], REG_W[1], REG_W[2], REG_W[3], REG_W[4], REG_W[5], REG_W[6], REG_W[7], REG_Z[0], REG_Z[1], REG_Z[2], REG_Z[3], REG_Z[4], REG_Z[5], REG_Z[6], REG_Z[7] (16 total)

DRFF_REG_IE_BIT

Single-edge-triggered semi-dynamic data flip-flop with active-high semi-asynchronous reset.

There is one external connection always made on this cell (see orange line in the picture) that is required to connect the two RESET inputs.

I/O Description D Data input. Gets stored in the flip-flop when CLK and RESET are both low and LOAD is high. However, the new data is only visible at the outputs Q and Q after a positive edge on CLK. CLK Positive clock input. Edge sensitive for presenting stored data at output; level sensitive for taking new data from input into storage. When CLK and RESET are both low and LOAD is high, the data input D gets stored in the flip-flop. After a positive edge on CLK, the newly stored data is visible at the outputs Q and Q. CLK must not be held low for an extended amount of time, otherwise the stored data will decay. CLK Negative clock input. Must always be the inverse of CLK. LOAD Active-high load input. Input D gets stored in the flip-flop when LOAD is high and CLK and RESET are both low. LOAD Active-low load input. Must always be the inverse of LOAD. RESET Active-high reset input. Data inside the flip-flop gets reset to 0 when RESET is high. However, the change is not (yet) visible at the outputs Q and Q while CLK is low. There are two RESET inputs to this cell, which are externally connected to each other (indicated by the orange line in the picture). Q Data output. Q Inverted data output.

Instances: REG_IE[0], REG_IE[1], REG_IE[2], REG_IE[3], REG_IE[4], REG_IE[5], REG_IE[6], REG_IE[7] (8 total)

DSFF_REG_PC_BIT

Single-edge-triggered semi-dynamic data flip-flop with precharge and active-low semi-asynchronous set.

There is one external connection always made on this cell (see orange line in the picture) that is required to connect the two SET inputs.

I/O Description D Data input. Gets stored in the flip-flop when CLK is low and LOAD and SET are both high. However, the new data is only visible at the outputs Q and Q after a positive edge on CLK. PCH Active-low precharge input. If low, D gets driven high for the purpose of precharging the net connected to the input. CLK Positive clock input. Edge sensitive for presenting stored data at output; level sensitive for taking new data from input into storage. When CLK is low and LOAD and SET are both high, the data input D gets stored in the flip-flop. After a positive edge on CLK, the newly stored data is visible at the outputs Q and Q. CLK must not be held low for an extended amount of time, otherwise the stored data will decay. CLK Negative clock input. Must always be the inverse of CLK. LOAD Active-high load input. Input D gets stored in the flip-flop when LOAD and SET are both high and CLK is low. LOAD Active-low load input. Must always be the inverse of LOAD. SET Active-low set input. Data inside the flip-flop gets set to 1 when SET is low. However, the change is not (yet) visible at the outputs Q and Q while CLK is low. There are two SET inputs to this cell, which are externally connected to each other (indicated by the orange line in the picture). Q Data output. Q Inverted data output.

Instances: REG_PCH[0], REG_PCH[1], REG_PCH[2], REG_PCH[3], REG_PCH[4], REG_PCH[5], REG_PCH[6], REG_PCH[7], REG_PCL[0], REG_PCL[1], REG_PCL[2], REG_PCL[3], REG_PCL[4], REG_PCL[5], REG_PCL[6], REG_PCL[7] (16 total)