DMG-CPU SM83 Core Connections

This is a list of all connections to/from the SM83 CPU core as seen in the Gameboy DMG-CPU-B die shot. The wire and cell names are taken from our schematics of the DMG-CPU B. We inherited the cell names from Furrtek's schematics, the wire names though are mostly different to his.

For a deeper understanding of the CPU, you should have a look at the reverse engineering efforts of ogamespec and Gekkio.

Please report any errors I made here.

SM83 "Pinout"

SM83 CPU core inside Game Boy DMG-CPU B chip

SM83 Connections

I/O		Name	Wire	Cell	Description
T1	O	M1	M1	LEXY.in	Machine cycle one (M1) synchronization signal. The output of the inverter LEXY ends at an output pad at the bottom of the die, which is not bonded. It is high during the instruction fetch cycle (M1). TODO: Figure out exact timing.
T2	I	ADR_CLK_N	BOWA	BOWA.q	A gated 1 MiHz clock, which goes low the moment the CPU outputs the new address at the beginning of a memory cycle. It is low while the address is valid on the cartridge port and high during the short time when the address high byte on the cartridge port is usually zeroed. The CPU can stop this clock by driving T11 or T14 low. This is the inverse of T3.
T3	I	ADR_CLK_P	DATA_VALID	BEDO.q	A gated 1 MiHz clock, which goes high the moment the CPU outputs the new address at the beginning of a memory cycle. It is high while the address is valid on the cartridge port and low during the short time when the address high byte on the cartridge port is usually zeroed. The CPU can stop this clock by driving T11 or T14 low. This is the inverse of T2.
T4	I	PHI_CLK_P	CPU_PHI	BEKO.q, BAVY.q	A gated 1 MiHz clock, which is identical to the 1 MiHz PHI clock signal on the cartridge port. The CPU can stop this clock by driving T11 low. This is the inverse of T5.
T5	I	PHI_CLK_N	CPU_PHI	BUDE.q, BEVA.q	A gated 1 MiHz clock, which is the inverse of the 1 MiHz PHI clock signal on the cartridge port. The CPU can stop this clock by driving T11 low. This is the inverse of T4.
T6	I	T4_CLK_N	CPU_T4	BOLO.q, BYDA.q	A gated 1 MiHz clock, which is low during the fourth quarter of each memory cycle. The CPU can stop this clock by driving T11 low. This is the inverse of T7.
T7	I	T4_CLK_P	CPU_T4	BUFA.q, BYLY.q	A gated 1 MiHz clock, which is high during the fourth quarter of each memory cycle. The CPU can stop this clock by driving T11 low. This is the inverse of T6.
T8	I	?	BUKE	BUKE.q	A gated 1 MiHz clock, which goes high when T7 goes high, and low when T2 and T10 go low. The CPU can stop this clock by driving T11 low. This is the only clock that goes into the CPU that has no inverse counterpart.
T9	I	MAIN_CLK_N	BOMA_1MHZ	BOMA.q	A gated 1 MiHz clock, which goes high the moment the CPU outputs the new address at the beginning of a memory cycle. It is high while the address is valid on the cartridge port and low during the short time when the address high byte on the cartridge port is usually zeroed. The CPU can stop this clock by driving T14 low. This is the inverse of T10. T9 and T10 are the only clock inputs that are ticking during HALT mode.
T10	I	MAIN_CLK_P	BOGA_1MHZ	BOGA.q	A gated 1 MiHz clock, which goes low the moment the CPU outputs the new address at the beginning of a memory cycle. It is low while the address is valid on the cartridge port and high during the short time when the address high byte on the cartridge port is usually zeroed. The CPU can stop this clock by driving T14 low. This is the inverse of T9. T9 and T10 are the only clock inputs that are ticking during HALT mode.
T11	O	CLK_ENA	CLK_ENA	ABOL.in, TUBO.s	CPU can drive this low to disable most of the clocks fed to itself. T9 and T10 are the only clocks that are not turned off when this signal gets driven low. However, T9 and T10 might have slightly shorter "shorter" phases while this signal is high. By "shorter" phases I mean, they are not symetric and have a shorter and a longer phase (and the shorter one gets even shorter). This is because of BUTO mixing them with the other clocks when they're active. Maybe they did this to guarantee a specific synchronicity between T9/T10 and the other clocks that tick at around the same time as T9/T10. The initial state (during and directly after reset) of T11 must be low. The CPU must NOT switch this signal to high immediately after reset, otherwise the synchronous CPU reset T12 (AFER) and the synchronous peripheral resets (RESET2, APU_RESETn, PPU_RESETn, ...) will never be deasserted. The CPU must wait until T15 (TABA) gets high. This happens when the DIV register is half run through, which takes about 32 milliseconds. Then the CPU can pull T11 high, which deasserts the synchronous CPU and peripheral resets one T9/T10 tick later. Wether the CPU pulls T11 high immediately when T15 gets high or if it delays that by a T9/T10 tick is unknown (both will work fine). I assume this mechanism is there to assure the crystal oscillator is stabilized. The same mechanism likely is used when the system wakes up from STOP mode. When the crystal oscillator gets disabled by driving T14 low, the DIV register gets reset to zero, so it will take the same ~32 ms. When the CPU executes a HALT instruction and none of the enabled interrupts are pending, then the CPU will pull T11 low to disable most of its clocks. When waking up from HALT mode (due to an interrupt), the CPU will pull T11 high on the next T9/T10 tick, which re-enables all the other clocks.
T12	I	SYNC_RESET	RESET_LATCH	AFER.q	Active-high synchronous reset input. Synchronized to T9/T10.
T13	I	ASYNC_RESET	RESET	RESET	Active-high asynchronous reset input. Fed directly from RESET input pad.
T14	O	OSC_ENA	OSC_ENA	multiple	Crystal oscillator enable. When CPU drives this low, the crystal oscillator gets disabled to save power. This happens during STOP mode.
T15	I	OSC_STABLE	OSC_STABLE	TABA.q	Active-high crystal oscillator stablilized input? After reset, this signal gets high after about 32 milliseconds. The CPU must not drive T11 high before T15 gets high. See description of T11.
T16	I	NMI	NMI	NMI	Directly connected to an input pad at the top of the die, which is not bonded. This is the non-maskable interrupt of the CPU.
R1	O	RD	READ	multiple	Active-high memory RD signal from CPU.
R2	O	WR	WRITE	multiple	Active-high memory WR signal from CPU.
R3	I	?	T1T2	UNOR.q	Maybe used to disable all bus drivers in the CPU when test mode is active.
R4	I	?	FEXX_FFXX	SYRO.q	High when address bus is 0xfexx or 0xffxx. When high, it suppresses R7, so that the data bus can be driven by an internal component (HRAM, OAM, FFxx registers).
R5	I	?	BOOT_SEL	TUTU.q	High when address bus is 0x00xx and boot ROM is still visible. When high, it suppresses R7, so that the data bus can be driven by the internal boot ROM.
R6	I	?	T1T2	UMUT.q	Maybe used to disable all bus drivers in the CPU when test mode is active.
R7	O	MREQ	MREQ	TEXO.in1, AGUT.in3	Active-high external memory request. Has to be high during external memory cycles (read or write). This causes one of the chip select signals (CS, MCS, A15) to be asserted in the right moment. Has to be low if no memory cycle is going on, otherwise the chip select will be asserted even if R1 and R2 are low. During write cycles, this signal is also needed for driving the internal data bus onto the external I/O pins. During read cycles, this signal is also needed for latching the external I/O pins and driving the latched data onto the internal data bus. When R4 or R5 is high, the CPU keeps this signal low, allowing internal components (HRAM, OAM, boot ROM, FFxx registers) to drive the internal data bus.
R8	?	?	-	-	Not connected.
R9	?	?	-	-	Not connected.
R10	?	?	-	-	Not connected.
R11	?	?	-	-	Not connected.
R12	?	?	-	-	Not connected.
R13	O	IE_SEL	-	-	Not connected. High when interrupt enable register is selected (ADR=0xFFFF).
R14	O	IRQ0_ACK	CPU_IRQ_ACK0	LETY.in	Active-high. Acknowledges IRQ0 (V-Blank).
R15	I	IRQ0	CPU_IRQ0	LOPE.q	Active-high. Triggers IRQ0 (V-Blank).
R16	O	IRQ1_ACK	CPU_IRQ_ACK1	LEJA.in	Active-high. Acknowledges IRQ1 (Status).
R17	I	IRQ1	CPU_IRQ1	LALU.q	Active-high. Triggers IRQ1 (Status).
R18	O	IRQ2_ACK	CPU_IRQ_ACK2	LESA.in	Active-high. Acknowledges IRQ2 (Timer).
R19	I	IRQ2	CPU_IRQ2	NYBO.q	Active-high. Triggers IRQ2 (Timer).
R20	O	IRQ3_ACK	CPU_IRQ_ACK3	LUFE.in	Active-high. Acknowledges IRQ3 (Serial).
R21	I	IRQ3	CPU_IRQ3	UBUL.q	Active-high. Triggers IRQ3 (Serial).
R22	O	IRQ4_ACK	CPU_IRQ_ACK4	LAMO.in	Active-high. Acknowledges IRQ4 (Joypad).
R23	I	IRQ4	CPU_IRQ4	ULAK.q	Active-high. Triggers IRQ4 (Joypad).
R24	O	IRQ5_ACK	CPU_IRQ_ACK5	-	Active-high. Acknowledges IRQ5. Not connected.
R25	I	IRQ5	GND	-	Active-high. Triggers IRQ5. Hardwired to GND.
R26	O	IRQ6_ACK	CPU_IRQ_ACK6	-	Active-high. Acknowledges IRQ6. Not connected.
R27	I	IRQ6	GND	-	Active-high. Triggers IRQ6. Hardwired to GND.
R28	O	IRQ7_ACK	CPU_IRQ_ACK7	-	Active-high. Acknowledges IRQ7. Not connected.
R29	I	IRQ7	GND	-	Active-high. Triggers IRQ7. Hardwired to GND.
B1	I/O	D0	D0	multiple	Data bus D0.
B2	I/O	D1	D1	multiple	Data bus D1.
B3	I/O	D2	D2	multiple	Data bus D2.
B4	I/O	D3	D3	multiple	Data bus D3.
B5	I/O	D4	D4	multiple	Data bus D4.
B6	I/O	D5	D5	multiple	Data bus D5.
B7	I/O	D6	D6	multiple	Data bus D6.
B8	I/O	D7	D7	multiple	Data bus D7.
B9	O	A15	A15	multiple	Address bus A15.
B10	O	A14	A14	multiple	Address bus A14.
B11	O	A13	A13	multiple	Address bus A13.
B12	O	A12	A12	multiple	Address bus A12.
B13	O	A11	A11	multiple	Address bus A11.
B14	O	A10	A10	multiple	Address bus A10.
B15	O	A9	A9	multiple	Address bus A9.
B16	O	A8	A8	multiple	Address bus A8.
B17	O	A7	A7	multiple	Address bus A7.
B18	O	A6	A6	multiple	Address bus A6.
B19	O	A5	A5	multiple	Address bus A5.
B20	O	A4	A4	multiple	Address bus A4.
B21	O	A3	A3	multiple	Address bus A3.
B22	O	A2	A2	multiple	Address bus A2.
B23	O	A1	A1	multiple	Address bus A1.
B24	O	A0	A0	multiple	Address bus A0.
B25	I	WAKE	CPU_WAKEUP	AWOB.q	Wakes CPU from STOP mode.