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DMG-CPU Cells Reference

This document provides information about the cells found in the Gameboy DMG-CPU-B die shot. It builds on the work of Furrtek, the information found in his DMG-CPU-Inside repository.

I was in the process of tracing back all the connections from the CPU and was constantly encountering cells for which the cell zoo JPG wasn't providing the pinout, so I wanted to have them all documented once and for all, to make life easier!

Please report any errors I made here.

Basic logic gates

INVERTER gates

INVERTER - Variant A

Simple inverter.

I/ODescription
in Input to inverter.
q Outputs inverted in.

INVERTER - Variant B

Inverter with higher driving strength.


I/ODescription
in Input to inverter.
q Outputs inverted in.

INVERTER - Variant C

Inverter with higher driving strength.

I/ODescription
in Input to inverter.
q Outputs inverted in.

INVERTER - Variant D

Inverter with higher driving strength.

I/ODescription
in Input to inverter.
q Outputs inverted in.

INVERTER - Variant E

Inverter with higher driving strength.

I/ODescription
in Input to inverter.
q Outputs inverted in.

NAND gates

NAND2

NAND gate with two inputs.

I/ODescription
in1, in2 Inputs to NAND gate.
q Outputs !(in1 && in2).

NAND3

NAND gate with three inputs.

I/ODescription
in1, in2, in3 Inputs to NAND gate.
q Outputs !(in1 && in2 && in3).

NAND4

NAND gate with four inputs.

I/ODescription
in1, in2, in3, in4 Inputs to NAND gate.
q Outputs !(in1 && in2 && in3 && in4).

NAND5

NAND gate with fife inputs.

I/O

Description

in1, in2, in3, in4, in5 Inputs to NAND gate.
q Outputs !(in1 && in2 && in3 && in4 && in5).

NAND6

NAND gate with six inputs.

I/ODescription
in1, in2, in3, in4, in5, in6 Inputs to NAND gate.
q Outputs !(in1 && in2 && in3 && in4 && in5 && in6).

NAND7

NAND gate with seven inputs.

I/ODescription
in1, in2, in3, in4, in5, in6, in7 Inputs to NAND gate.
q Outputs !(in1 && in2 && in3 && in4 && in5 && in6 && in7).

NOR gates

NOR2

NOR gate with two inputs.

I/ODescription
in1, in2 Inputs to NOR gate.
q Outputs !(in1 || in2).

NOR3

NOR gate with three inputs.

I/ODescription
in1, in2, in3 Inputs to NOR gate.
q Outputs !(in1 || in2 || in3).

NOR4

NOR gate with four inputs.

I/ODescription
in1, in2, in3, in4 Inputs to NOR gate.
q Outputs !(in1 || in2 || in3 || in4).

NOR5

NOR gate with five inputs.

I/ODescription
in1, in2, in3, in4, in5 Inputs to NOR gate.
q Outputs !(in1 || in2 || in3 || in4 || in5).

NOR6

NOR gate with six inputs.

I/ODescription
in1, in2, in3, in4, in5, in6 Inputs to NOR gate.
q Outputs !(in1 || in2 || in3 || in4 || in5 || in6).

NOR8

NOR gate with eight inputs.

I/ODescription
in1, in2, in3, in4, in5, in6, in7, in8 Inputs to NOR gate.
q Outputs !(in1 || in2 || in3 || in4 || in5 || in6 || in7 || in8).

AND gates

AND2

AND gate with two inputs.

I/ODescription
in1, in2 Inputs to AND gate.
q Outputs (in1 && in2).

AND3

AND gate with three inputs.

I/ODescription
in1, in2, in3 Inputs to AND gate.
q Outputs (in1 && in2 && in3).

AND4

AND gate with four inputs.

I/ODescription
in1, in2, in3, in4 Inputs to AND gate.
q Outputs (in1 && in2 && in3 && in4).

OR gates

OR2

OR gate with two inputs.

I/ODescription
in1, in2 Inputs to OR gate.
q Outputs (in1 || in2).

OR3

OR gate with three inputs.

I/ODescription
in1, in2, in3 Inputs to OR gate.
q Outputs (in1 || in2 || in3).

OR4

OR gate with four inputs.

I/ODescription
in1, in2, in3, in4 Inputs to OR gate.
q Outputs (in1 || in2 || in3 || in4).

XNOR

XNOR gate with two inputs.

I/ODescription
in1, in2 Inputs to XNOR gate.
q Outputs !(in1 ^ in2).

XOR

XOR gate with two inputs.

I/ODescription
in1, in2 Inputs to XOR gate.
q Outputs (in1 ^ in2).

Compound logic gates

AOI1

2-1 AND-OR-INVERT two-level compound gate.

Name in DMG-CPU-Inside: NAO

I/ODescription
a, b Inputs to AND gate.
c Input to OR gate.
q Outputs !((a && b) || c).

AOI2

2-2 AND-OR-INVERT two-level compound gate.

Name in DMG-CPU-Inside: AOI_MUX_2

I/ODescription
a, b; c, d Inputs to AND gates.
q Outputs !((a && b) || (c && d)).

AOI3

2-2-2 AND-OR-INVERT two-level compound gate.

Name in DMG-CPU-Inside: AOI_MUX_3

I/ODescription
a, b; c, d; e, f Inputs to AND gates.
q Outputs !((a && b) || (c && d) || (e && f)).

AOI4

2-2-2-2 AND-OR-INVERT two-level compound gate.

Name in DMG-CPU-Inside: AOI_MUX_4

I/ODescription
a, b; c, d; e, f; g, h Inputs to AND gates.
q Outputs !((a && b) || (c && d) || (e && f) || (g && h)).

AOI6

2-2-2-2-2-2 AND-OR-INVERT two-level compound gate.

Name in DMG-CPU-Inside: AOI_MUX_6

I/ODescription
a, b; c, d; e, f; g, h; i, j; k, l Inputs to AND gates.
q Outputs !((a && b) || (c && d) || (e && f) || (g && h) || (i && j) || (k && l)).

AO

2-1 AND-OR two-level compound gate.

Name in DMG-CPU-Inside: AO3

I/ODescription
a, b Inputs to AND gate.
c Input to OR gate.
q Outputs ((a && b) || c).

OA

2-1 OR-AND two-level compound gate.

Name in DMG-CPU-Inside: OA3

I/ODescription
a, b Inputs to OR gate.
c Input to AND gate.
q Outputs ((a || b) && c).

MUXI

Inverting multiplexer with two inputs.

I/ODescription
d0, d1 Data inputs.
sel Select input.
q Outputs inverted d0 if sel is high; outputs inverted d1 if sel is low.

MUX

Multiplexer with two inputs.

I/ODescription
d0, d1 Data inputs.
sel Select input.
q Outputs d0 if sel is high; outputs d1 if sel is low.

Arithmetic gates

HALF_ADD

Half adder.

I/ODescription
a, b Summand inputs.
cout Carry output. Outputs (a && b).
q Sum output. Outputs (a ^ b).

FULL_ADD

Full adder.

I/ODescription
a, b Summand inputs.
cin Carry input.
cout Carry output. Outputs ((a && b) || (cin && (a ^ b))).
q Sum output. Outputs (a ^ b ^ cin).

Tri-state buffers

TRIBUFFER - Variant A

Tri-state buffer, inverting.

This cell comes in two very similar looking shapes: One has an active-high enable input; the other has an active-low enable input.


I/ODescription
in Input.
ena Active-high enable input. When high, the value at in gets inverted at !q. When low, !q is not driven.
!ena Active-low enable input. When low, the value at in gets inverted at !q. When high, !q is not driven.
!q Inverted tri-state output.

TRIBUFFER - Variant B

Tri-state buffer, non-inverting with active-low enable input.

There is one external connection always made on this cell (see pink line in the picture) that seem to be necessary for it to work.

I/ODescription
in Input. There are two inputs to this cell, which are externally connected to each other (by the pink line in the picture).
!ena Active-low enable input. When low, the value at in gets passed through to q. When high, q is not driven.
q Tri-state output. (Not inverted!)

Instances: AJOV AKAN ANAR AZUV BYNA BYNE BYXE DEVE FYRA KEJO LEFY LOFA LORA LYNA MAPU NEFE RALA ROPA RUJO SAJO SEDU SEKE SOSA SOTE SUGU SUZA SYWA SYZU TAHY TAWO TAXO TAZU TEME TEMY TESU TEWA TEWU TOFA TOVU TUTE TUTY TYGO XABU XACA XAGU XELE XEPU XUNA XUVO XYGU YFAP YPON YTUX YWEG ZEHA ZYSA

Storage elements

SR-LATCH

Set/reset latch.

These are wrongly labelled OR and AND gates in the schematics. Rgalland just figured out the correct function of these cells.


I/ODescription
s Set input. When high, latch is set to 1.
r Reset input. When high, latch is reset to 0.
!s Inverted set input. When low, latch is set to 1.
!r Inverted reset input. When low, latch is reset to 0.
q Data output.
!q Inverted data output.

DLATCH

Gated data latch.

Name in DMG-CPU-Inside: LATCH

I/ODescription
d Data input.
ena Active-high enable input. When high, the value at d transparently propagates through the latch. As soon as ena goes low, the output of the latch gets held at the level it had in that moment until ena goes high again.
q Data output.
!q Inverted data output.

DFF

Single-edge-triggered data flip-flop.

There are two clock inputs to this cell. They need to be inverted towards each other. There is usually an inverter cell nearby that generates the inverted clock. The flip-flop triggers on a positive edge of clk and a negative edge of !clk.

There are instances of this cell that have their !q output stripped off. Those stripped cells can have an unrelated net run through the row where the !q output would have been. The cells named MYTU and MOFO are two examples of that.

Name in DMG-CPU-Inside: DFF2

I/ODescription
d Data input. Gets stored in the flip-flop on positive edge of clk and a simultanious negative edge of !clk.
clk Positive clock input. On a positive edge the data input d gets stored in the flip-flop. There needs to be a negative edge on the !clk input at the same time.
!clk Negative clock input. On a negative edge the data input d gets stored in the flip-flop. There needs to be a positive edge on the clk input at the same time.
q Data output.
!q Inverted data output.

Instances with !q: ABEG ABOP ABUG ABUX ACEP AFUT AFYM AFYX AMES ANED APEV AROF AXUV AZAP BADA BADO BAXO BECA BEXY BOXA BOZU BUHE BULU BUNA BYHE BYHU CADU CAJU CAJY CANA CAPO CEBO COMA CONO CUFA CUFO CUMU CUZA DAFU DEBA DEPO DESE DEVY DEWU DUHA DUNY DYSY EBEX EKAP EKOP ETAV ETYM FEFA FOFO FOGO FOXY FUZO FYHY FYSU GABO GACY GECU GESY GOHU GOMO GORU GULE GYHO GYNO LAWO LEPU LOSE LUGU LUNE LUXO MARU MAXY MENA MOGY MORU MOSA MOXY MUKE NAFA NUSY NYDO NYGY PARA PAVO POKU PULA PYLU PYNE WANU WYSO WYTE XABO XAKU XALO XANA XAVE XAZY XEFE XEGE XEGU XERU XOSY XOTE XOTU XOVA XUFO XUFU XUKY XUPO XUSO XUTE XYFE XYGO XYJU XYNA XYNU XYZE YBER YBOG YGUM YGUS YJEX YKUK YLOR YLOV YSOK YWAK YZAB YZEP YZOR YZOS ZAFU ZENE ZEXO ZEZY ZONY ZUBE ZUMY ZURO ZURY ZYLU ZYTY ZYVE

Instances without !q: LEGU LUZO MEGU MOFO MUKU MYJY MYTU NASA NEFO NUDU PEBA PEFO PUDU RAMA RAMU REWO ROKA RYDU SAJA SEGA SELE SEMO SUNY SUTO

DFFR - Variant A

Single-edge-triggered data flip-flop with active-low asynchronous reset.

There are two clock inputs to this cell. They need to be inverted towards each other. There is usually an inverter cell nearby that generates the inverted clock. The flip-flop triggers on a positive edge of clk and a negative edge of !clk. It doesn't seem to matter which one of the two inputs gets slightly delayed by the inverter, it works both ways.

TODO: Not really sure about clock input polarity.

Name in DMG-CPU-Inside: DTFF

I/ODescription
d Data input. Gets stored in the flip-flop on positive edge of clk and a simultanious negative edge of !clk.
clk Positive clock input. On a positive edge the data input d gets stored in the flip-flop. There needs to be a negative edge on the !clk input at the same time.
!clk Negative clock input. On a negative edge the data input d gets stored in the flip-flop. There needs to be a positive edge on the clk input at the same time.
!rst Active-low reset input. Data inside the flip-flop gets reset to 0 when !rst is low.
q Data output.
!q Inverted data output.

Instances: ADEK ADYK AFUR AGER ALEF ANAZ ANEV APEG APOS APUK ARAX ATUF AVAF BAFO BAKE BAMY BANA BANY BEDU BEFO BEGU BEMY BEPA BEPU BERA BOFA BOGU BOKO BORA BOTU BUDY BUME BUMO BYGA BYRE CABU CENA CESO CESY CEVO COZU CUNY CUSY CUVO CUVY CUZY CYFO CYWE CYXU DAKE DANY DATY DAZO DEDE DEPY DESU DUHY DUKO DUPE DURY DUZU DYBY DYCA DYFU EBOW EHYN EJUF EMER EMOK ENAD ENOR EPUM ERAZ EROL ETAP ETYJ EXUK EZUF EZYK FAXA FAXE FAZU FEDE FEDY FERO FESY FETA FEZU FOFE FOHA FOKA FOME FORA FORE FOTY FOVA FOZY FUBY FUJO FUNY FUSA FYCA FYMO FYTO FYTY GADY GAFO GAGE GARU GATA GAVE GAVU GAVY GAZA GEDU GEKY GODA GOGO GOKY GOXU GOZO GUBO GUFE GUMY GUPU GURA GUXE GYPU HAVA HODY HOGA HORE HOTO HUKY HYFU JACY JAFY JAKY JAMY JANY JARE JATY JAXA JAXO JEFE JEFU JEMO JENA JERO JETY JOMA JOPU JOVE JOVY JUPY JUSA JUZY JYPO KANA KOGA KOGU MEBY MELA MUVO MYCE MYPA MYPU NAFU NAGA NENE NESO NOFE NOKE NUKA NUKU NULO NYRO RAHA REFE ROXE RUFO RUGU SALO SEDY SOTA SYRY VAFA VEVO VUCE VYXE WECO WEDU WELO WEXU WOKY WOTE WUHA WYDE WYMO WYNA XABE XAFO XAKO XECY XEKA XEPA XEPE XERE XEXA XOMY XONA XOLY XUNY XURY XUVY XUZO XYBA XYLO XYMO YBED YCOL YGAJ YLAH YMEM YNEP YPOD YRAC YROP YVAG YZOF ZALA ZECU ZESA ZOGO ZOLA ZOLY ZULU ZYJO

DFFR - Variant B

Single-edge-triggered data flip-flop with active-low asynchronous reset.

There are two clock inputs to this cell. They need to be inverted towards each other. There is usually an inverter cell nearby that generates the inverted clock. The flip-flop triggers on a positive edge of clk and a negative edge of !clk. Sometimes the clock inputs are driven by the q and !q outputs of another flip-flop of the same variant.

There is one external connection always made on this cell (see pink line in the picture) that seem to be necessary for it to work.

Name in DMG-CPU-Inside: DTFF

I/ODescription
d Data input. Gets stored in the flip-flop on positive edge of clk and a simultanious negative edge of !clk.
clk Positive clock input. On a positive edge the data input d gets stored in the flip-flop. There needs to be a negative edge on the !clk input at the same time. See also here.
!clk Negative clock input. On a negative edge the data input d gets stored in the flip-flop. There needs to be a positive edge on the clk input at the same time. See also here.
!rst Active-low reset input. Data inside the flip-flop gets reset to 0 when !rst is low. There are two !rst inputs to this cell, which are externally connected to each other (by the pink line in the picture).
q Data output.
!q Inverted data output.

Instances: AFER CAGY DAPE DYVE EROS XADU XECU XEDY XOBE YDUF ZUZE

DFFR - Variant B+

Positive-edge-triggered data flip-flop with active-low asynchronous reset.

This cell is basically the same as variant B but with an extension at the top. This extension seems to generate the inverted clock that is required.

There are three external connections always made on this cell (see cyan, green and pink lines in the picture) that seem to be necessary for it to work. The cyan and green connections feed the positive and negative clocks generated by the extension to where they would be connected to if this was a cell of variant B without extension. There is not a single instance of this cell that has those two clock connections crossed, which means all instances trigger on a positive clock edge.

Name in DMG-CPU-Inside: DTFF

I/ODescription
d Data input. Gets stored in the flip-flop on positive edge of clk.
clk Clock input. On a positive edge the data input d gets stored in the flip-flop. See also here.
!rst Active-low reset input. Data inside the flip-flop gets reset to 0 when !rst is low. There are two !rst inputs to this cell, which are externally connected to each other (by the pink line in the picture).
q Data output.
!q Inverted data output.

Instances: ABEL ACEF AGEM AJER AMUT ANEL APUG ATEP ATYK AVOK AZET AZUS BANO BARA BATU BAZA BEGO BESE BEXA BOWY BURO BUSA BYBA BYLU BYTE CAFA CALO CALY CANO CARU CATU CAZA CEDY CEMO CENO CERO CERY CEXO COFY COMY COTY CULY CUXY CYDE CYLO CYRE DALE DAVO DEKO DEMO DERE DETE DEZY DOBA DOKE DOME DOPE DORY DOSE DOTA DURE DUWO DYBE EBOJ EFAL EFAR EFUZ EGAV ELOX ELYN ELYS EPOR ERUS ERUT ESEP ESUT ETAF EXEL EXUQ EZEC EZEF FAHA FARE FEKU FETY FEXU FOBA FONO FONY FOSY FUGO FYNO FYTE GARA GARY GATY GONE GORA GOSO GOTA GYKO GYRA GYSU GYTA HADA HAPE HENO HEPA HEPO HEZU HORY HUNO HYRO JAJU JALE JAVO JEPE JESO JOPA JOTO JUTE JUXE JYNA KALY KECY KELY KERU KETU KOMU KOZY KUKO KUTA KUZY KYME KYNO KYWY LAFO LAXU LEBE LEMA LENE LEXA LOVU LOVY LUCA LUVY LYDO LYZU MAKA MATO MATU MEDA MESU MOBA MUGU MURU MUTY MUWY MYTA MYTE MYRO NAKY NAPO NEFY NOPA NUNU NUTO NYDU NYKA NYKE NYKO NYPE NYVA NYZE PAHO PETO POPU PORY PUXA PYCO PYGO PYLO PYRO RENE ROGA ROPO RUBU RUTU RYFA RYKU SABO SABU SAMY SARY SAVY SAXO SEBA SETA SOBU SOLA SOPU SOTO SOVY SUBU SUDA SUDE SUFY SYBE SYGU TAHA TAKO TAMA TATE TAXA TEKA TEKE TELU TERO TERU TESE TEPU TOBU TOFE TOZO TOXE TUFU TUGO TUHU TUKY TULU TULY TYFO TYPO TYRU TYRY TYVA UFOR UGOT UKET UKUP UNER UNYK UPOF VENA VOGA VONU VUJO VYMU VYNO VYZO WAFY WAPO WEWY WOBO WODY WOMY WOSU WUVU WYKA WYKO XEHO XODU XOLO XUDY XUVA XYDO YFEL

DFFR - Variant C

Single-edge-triggered data flip-flop with active-low asynchronous reset.

re are two clock inputs to this cell. They need to be inverted towards each other. There is usually an inverter cell nearby that generates the inverted clock. The flip-flop triggers on a positive edge of clk and a negative edge of !clk.

There is one external connection always made on this cell (see pink line in the picture) that seem to be necessary for it to work.

This variant is similar to variant B, but it is missing the q output. Furthermore, it is one row shorter: There is only a single row between !rst and !q instead of two.

TODO: Not really sure about clock input polarity.

Name in DMG-CPU-Inside: DTFF

I/ODescription
d Data input. Gets stored in the flip-flop on positive edge of clk and a simultanious negative edge of !clk.
clk Positive clock input. On a positive edge the data input d gets stored in the flip-flop. There needs to be a negative edge on the !clk input at the same time.
!clk Negative clock input. On a negative edge the data input d gets stored in the flip-flop. There needs to be a positive edge on the clk input at the same time.
!rst Active-low reset input. Data inside the flip-flop gets reset to 0 when !rst is low. There are two !rst inputs to this cell, which are externally connected to each other (by the pink line in the picture).
!q Inverted data output.

Instances: DEFA DELE DEVA DEXE DOFY DOLY EDOK EPYR ETER EXAP FAXO GALO GELE GYME HELE HOPA HORA JAPE JETE JODE JYME KARE POJU POWY POXA POZO PULO PYJU PYZO RAWU

DFFSR

Positive-edge-triggered data flip-flop with active-low asynchronous set and reset.

There are four external connections always made on this cell (see orange, cyan, green and pink lines in the picture) that seem to be necessary for it to work.

Name in DMG-CPU-Inside: DFF3

I/ODescription
d Data input. Gets stored in the flip-flop on positive edge of clk.
clk Clock input. On a positive edge the data input d gets stored in the flip-flop. See also here.
!set Active-low set input. Data inside the flip-flop gets set to 1 when !set is low. There are two !set inputs to this cell, which are externally connected to each other (by the orange line in the picture).
!rst Active-low reset input. Data inside the flip-flop gets reset to 0 when !rst is low.
q Data output.
!q Inverted data output.

Instances: AXAN AGEZ BEKU CUBA DEGU DOJO DOVU DYGY DYRA EDER EDUL EJAB ELUX EROD EVAB EXAC FABU FEDO FELY FUDE GOGA HAVO HOLU HOPO HYKA HYXU JEFA JOLU JOTA JYKA LALU LEFE LESU LOPE LYME MACU MASO MODA MODU MOJU MYDE NATY NEDA NEPO NOZO NUKE NURO NYBO NYLU PALU PEFU PYBO PYJO RALU ROSA RUGO RYSA SADY SATA SETU SOBO SOHU SOMY TACA TOMY UBUL ULAK VAFO VANU VARE VAVA VEZO VOSA VUMO VUPY WEBA WODA WORA WUFY WURU WYFU WYHO XETE

TFFD

Negative-edge-triggered toggle flip-flop with active-high asynchronous data load.

This flip-flop is used for counters that can be loaded with a value.

There are four external connections always made on this cell (see orange, cyan, green and pink lines in the picture) that seem to be necessary for it to work.

Name in DMG-CPU-Inside: COUNT

I/ODescription
d Data input. Gets stored in the flip-flop when load is high. There are two d inputs to this cell, which are externally connected to each other (by the orange line in the picture).
!clk Clock input. On a negative edge the data inside the flip-flop gets inverted.
load Active-high load input. Input d gets stored in the flip-flop when load is high. There are two load inputs to this cell, which are externally connected to each other (by the cyan line in the picture).
q Data output.
!q Inverted data output.

Instances: AKYD BACY BOVY BUVA BYRA CAJA CAME CAVY CAXY CEDO CERA COFE CONU COPA COPU CUNA CUNO CUPO CURA CYPU CYVO DANO DENA DOGO DONE DYNU EDOP EKOV EMUS ERAM ERYC EVAK EZOF FATY FAVE FAVY FEKO FENA FENO FERU FETE FEVA FOMY FORO FORY FUXO FYLO FYRO FYRU GANE GANO GAPO GATU GAXE GEMO GEVO GOCA HAFO HEMY HEPU HERO HEVO HEVY HOKO HYFE HYKE JAPU JEMA JEVY JONA JORE JOVA JYCO JYFU JYRE JYTY KAFO KEJU KEMU KENO KENU KEPA KERA KEZA KUNU KUPE KUTU KYGU KYNA NUGA PEDA PERU POVY RAGE RATE REGA RUBY

I/O buffers

IOBUFFER - Variant A

Input/output buffer with open-drain/-source capability.

This cell is found all around the edge of the chip and is rotated (not mirrored!) so that the three connections face inwards.

I/ODescription
drv_low Drive low. When high, the I/O pad is actively driven low.
!drv_high Drive high. When low, the I/O pad is actively driven high.
!in Inverted input state. Reads the inverted binary level at the I/O pad.

Instances: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 MCS MOE MWR RD WR

IOBUFFER - Variant B

Input/output buffer with open-drain/-source capability and optional pull-up resistor.

This cell is found all around the edge of the chip and is rotated (not mirrored!) so that the four connections face inwards.

I/ODescription
drv_low Drive low. When high, the I/O pad is actively driven low.
!drv_high Drive high. When low, the I/O pad is actively driven high.
!weak_high Pull-up resistor. When low, a pull-up resistor is connected to the I/O pad.
!in Inverted input state. Reads the inverted binary level at the I/O pad.

Instances: D0 D1 D2 D3 D4 D5 D6 D7 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 P10 P11 P12 P13 SIN

IOBUFFER - Variant C

Input/output buffer with open-drain/-source capability and optional pull-up resistor.

This cell is only used for SCK. In the die shot this picture was taken from, this pin is located at the right-hand side. For consistency across this documentation it is rotated here (not mirrored!).

I/ODescription
drv_low Drive low. When high, the I/O pad is actively driven low.
!drv_high Drive high. When low, the I/O pad is actively driven high.
!weak_high Pull-up resistor. When low, a pull-up resistor is connected to the I/O pad.
!in Inverted input state. Reads the inverted binary level at the I/O pad.

Instances: SCK

IBUFFER

Simple inverting input buffer.

This cell is only used for RST, T1 and T2 (and an un-bonded unknown pad in the top-center of the die, that is directly connected to the CPU). In the die shot this picture was taken from, these pins (RST, T1 and T2) are located at the right-hand side. For consistency across this documentation it is rotated here (not mirrored!).

I/ODescription
!in Inverted input state. Reads the inverted binary level at the input pad.

Instances: RST T1 T2 [[unlabeled cell between A10 and A11]]

OBUFFER - Variant A

Simple inverting output buffer.

This cell is found all around the edge of the chip and is rotated (not mirrored!) so that the connection faces inwards.

I/ODescription
!out Output level. Output pad is driven high when !out is low, and it's driven low when !out is high. The pad is always actively driven.

Instances: CP CPG CPL CS FR LD0 LD1 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 PHI S SOUT ST [[unlabeled cell between LD0 and CPG]]

OBUFFER - Variant B

Output buffer with open-drain/-source capability.

This cell is only used for P14 and P15. In the die shot this picture was taken from, these pins are located in the bottom right corner. For consistency across this documentation it is rotated here (not mirrored!). Keep that in mind, especially for P14, where the !drv_high connection is at the top and drv_low is at the bottom.

I/ODescription
drv_low Drive low. When high, the output pad is actively driven low.
!drv_high Drive high. When low, the output pad is actively driven high.

Instances: P14 P15

OSC

Oscillator input and output pads for connecting external crystal.

This cell is only used for XI/XO. In the die shot this picture was taken from, these pins are located at the right-hand side. For consistency across this documentation it is rotated here (not mirrored!).

I/ODescription
clk Clock. Provides the source clock for the system. I suspect this input buffer to be inverting like the other input buffers.
ena Enable oscillator. This is driven low by the CPU core after encountering a STOP instruction to stop the crystal oscillator (to save power) until a button gets pressed.

Instances: XI/XO

AIBUFFER

Analog input buffer.

This cell is only used for VIN. In the die shot this picture was taken from, this pin is located at the bottom right. For consistency across this documentation it is rotated here (not mirrored!).

I/ODescription
vin Analog input. Reads the current analog level at the input pad.

Instances: VIN

AOBUFFER

Analog output buffer.

This cell is only used for ROUT and LOUT. In the die shot this picture was taken from, these pins are located at the bottom right. For consistency across this documentation it is rotated here (not mirrored!).

I/ODescription
vout Analog output. Drives the output pad based on this analog level. The pad is always actively driven.

Instances: LOUT ROUT

Other

SUPPLY

Constant supply.

The outputs of this cell are hardwired to VCC and GND. It is used to provide constant 1 and 0 signals to other cells. For example, it is used for the interrupt flags register: The PESU cell feeds a constant 1 into the data inputs of flip-flops (LOPE, UBUL, ...). Whenever the clock inputs of those flip-flops get triggered by an interrupt, the constant 1 gets clocked in.

I/ODescription
0 Constant 0 output. Connects to GND.
1 Constant 1 output. Connects to VCC.

Instances: PESU RUNY VYPO WEFE [[unlabeled cell between BONE and BUFY]]


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